1. Field of the Invention
The present invention relates to as emiconductor memory device having an optimized storage capacity.
2. Description of the Related Art
A conventional semiconductor memory device has an address space of 2.sup.n bits. Specifically, the address space has addresses from 0 to 2.sup.n -1, and one of the addresses from 0 to 2.sup.n -1 is to be specified by using an address signal of n bits. If each address in the address space corresponds to one bit of information, the semiconductor memory device has a storage capacity of 2.sup.n bits. A DRAM (Dynamic Random Access Memory), which is often used as a large capacity memory, is typically configurated in such a manner that each address corresponds to one bit of information.
In some cases, one may desire a semiconductor memory device having a storage capacity of 3.times.2.sup.n-1 bits obtained by adding 2.sup.n bits to 2.sup.n-1 bits which is half of 2.sup.n bits. Conventionally, such a semiconductor memory device has been implemented by either of the following methods: (1) combining a semiconductor memory device having a storage capacity of 2.sup.n bits with a semiconductor memory device having a storage capacity of 2.sup.n-1, and (2) using a single semiconductor memory device having a storage capacity of 2.sup.n+1. Since method (1) can be realized at lower costs than method (2), method (1) is more likely to be used in cases where costs are regarded as an important factor.
FIG. 12 shows a configuration for a conventional semiconductor memory device in which a semiconductor memory device 31 having a storage capacity of 2.sup.n bits and a semiconductor memory device 32 having a storage capacity of 2.sup.n-1 bits are combined. The semiconductor memory device 31 receives an address signal of n bits (A.sub.0 to A.sub.n-1). The semiconductor memory device 32 receives an address signal of (n-1) bits (A.sub.0 to A.sub.n-2). A chip enable signal CE1 and a chip enable signal CE2 are controlled in such a manner that only one of them is active at a time. When CE1 is active, the semiconductor memory device 31 is selected. As a result, data (D.sub.0 to D.sub.7) is read out from the semiconductor memory device 31 in accordance with the address signal of A.sub.0 to A.sub.n-1. When CE2 is active, the semiconductor memory device 32 is selected. As a result, data (D.sub.0 to D.sub.7) is read out from the semiconductor memory device 32 in accordance with the address signal of A.sub.0 to A.sub.n-2.
FIG. 13 shows a configuration for a semiconductor memory device which is composed of a single semiconductor memory device 33 having a storage capacity of 2.sup.n+1 bits. An address signal of (n+1) bits and a chip enable signal CE are input to the semiconductor memory device 33. When the chip enable signal CE is active, data (D.sub.0 to D.sub.7) is read out from the semiconductor memory device 33 in accordance with the address signal of A.sub.0 to A.sub.n.
The semiconductor memory devices 31 and 32 each have a plurality of signal terminals for receiving the address signals. The number of the signal terminals of each of the semiconductor memory devices 31 and 32 and the arrangement of the signal terminals are often different from the number signal terminals and terminal arrangement of a semiconductor memory device having a storage capacity of 2.sup.n+1 bits. This is because a different number of bits for an address signal to be input to a semiconductor memory device requires a different design of the semiconductor memory device, in general. Therefore, if a storage capacity of 2.sup.n+1 bits becomes necessary later, it is difficult to replace the semiconductor memory devices 31 and 32 with a semiconductor memory device having a storage capacity of 2.sup.n+1 bits. Thus, a conventional semiconductor memory device has the problem of poor expandability of storage capacity.
The semiconductor memory device shown in FIG. 13 has the advantages that (1) the circuitry used therein is of a simple configuration, and (2) the storage capacity can be expanded up to 2.sup.n+1 bits without particularly changing the circuitry configuration. However, the semiconductor memory device shown in FIG. 13 has the problem of increased costs, since it utilizes a semiconductor memory device having a maximum storage capacity larger than the storage capacity which is actually required.
Hereinafter, the increase in cost of a semiconductor memory device in the case where the storage capacity thereof is to be increased to be twice as large will be described.
FIG. 16A schematically shows the respective sizes of a 1M bit memory chip and a 2M bit memory chip. FIG. 16B schematically shows the respective sizes of a 16M bit memory chip and a 32M bit memory chip.
As is shown in FIG. 16A, the size of the memory chip mainly depends on the size of the peripheral circuitry when the storage capacity of the semiconductor memory device is relatively small. The size of the peripheral circuitry does not change drastically even if the number of the memory cells is doubled. Accordingly, the size of the memory chip does not change drastically even if the number of the memory cells is doubled. On the other hand, as is shown in FIG. 16B, the size of a memory chip having a relatively large storage capacity mainly depends on the number of the memory cells. Accordingly, the size of the memory chip increases substantially in proportion to the number of the memory cells. As a result, if the storage capacity of the semiconductor memory device is doubled, an area occupied by the memory chip is also substantially doubled, thereby substantially doubling the manufacturing costs of the memory chip. It is extremely important for a semiconductor memory device to be fabricated at low costs to have superiority over other semiconductor memory devices on the semiconductor memory device market. Accordingly, the semiconductor memory device shown in FIG. 13 is not desirable in terms of the fabrication costs.
The present invention, therefore, aims at providing a semiconductor memory device having an optimized storage capacity and an excellent expandability of storage capacity. Herein, the expression `optimized storage capacity` is defined as a storage capacity which is optimum in terms of the cost aspect as described above.
FIG. 17 illustrates yearly transitions of the costs of 8M bit memories, 16M bit memories, and 32M bit memories. It will be understood that the costs required for each class of memories are reduced every year, but that the costs for a 32M bit memory are still approximately twice as large as those for a 16M bit memory. This indicates that there may exist a potential need for, in the case where a storage capacity larger than 16M bits is required, a smaller storage capacity than 32M bits, such as 24M bits, because of the cost problem as described above.